1. Technical Field of the Invention
The present invention, in general, relates to the field of semiconductor integrated circuits. In particular, this invention relates to improving the compatibility of a Silicon-On-Insulator (SOI) type semiconductor substrate with different integrated circuit manufacturing technologies in the perspective of joining analog-digital mixed circuits onto the same substrate of the type mentioned above.
2. Description of Related Art
SOI (Silicon-On-Isolator) type substrates have been developed within the framework of the CMOS SOI technology.
As illustrated in diagram form in FIG. 1, an SOI substrate is normally composed of a very thin layer 10 of monocrystalline silicon, with a thickness of, for example, approximately 160 nm, separated from the substrate layer 20, for example made of silicon, by a layer 30 of buried insulating material (silicon oxide, for example), with a thickness of, for example, approximately 400 nm. Other pairs of silicon thicknesses and insulating oxide thicknesses are of course possible. SOI transistors are formed in the thin layer 10 of silicon, called the active layer. The active area of the transistor is therefore delimited laterally by a structure, for example, made of silicon oxide, encased in the surface of the active layer 10, which is currently designated in the technique by STI (Shallow Trench Isolation.)
Thanks to the buried oxide layer to be placed below the thin active layer of silicon, high-resistance substrates can be used. These substrates allow for reducing electric leaks and significantly decreasing the proximity parasite coupling between circuits created on the same substrate. This characteristic is particularly advantageous in the manufacturing of mixed analog-digital circuits on the same silicon chip, in particular, within the application framework that requires components operating at high frequencies. The SOI technology also allows for creating MOS type field effect transistors with greater dynamic characteristics than with respect to traditional CMOS technology (called bulk), in addition to presenting other specific advantages, such as a lower power supply voltage.
The potential capabilities of SOI technology therefore create a technology that is specifically adapted to high-performance applications that require low consumption, in particular, in the portable electronic device and wireless communications market.
Nevertheless, for these applications, the miniaturization of systems is heading towards integrated circuits that contain all of the functions included in a single chip, instead of having specific separate integrated circuits for creating each module. Currently, analog components that provide high-frequency, for example, bipolar transistors, are difficult to integrate into an SOI substrate.
Indeed, at the SOI substrate level, the active silicon layer, normally less than 200 mn, is much too thin to accommodate current vertical bipolar transistors. Thus, when such a transistor is to be operated at high frequency, it can be observed that one of the main limiting parameters resides in the low thickness of the active silicon layer. Therefore, the behavior of this type of component built on an SOI type substrate is thus modified, and in particular, their operating speed is degraded.
The behavior of other types of components is also modified when they are built on an SOI type based silicon substrate, which is normally adapted for CMOS components.
The specific structure of the SOI substrate therefore leads to its use being dedicated to CMOS technology. SOI use is not currently foreseeable for accepting all integrated circuit technologies because of the above-mentioned issues. This can be particularly damaging in the perspective of integrating mixed analog-digital circuits on the same SOI substrate.
To counter the limiting characteristics of the thinness of the active silicon layer for building certain devices, the thickness of this layer, whose thickness is normally fixed along the entire surface of the substrate, could be increased locally in places on the substrate where the devices in question must be placed. These variable thickness areas can be formed on the desired locations by selective epitaxial growth on the top active layer of the substrate. With this method, however, silicon steps (i.e., elevation changes) are obtained on the substrate surface.
In this way, an SOI substrate can be obtained that presents, at certain locations, a variable silicon thickness on the insulator. Nevertheless, the surface of the substrate thus obtained will no longer be flat, which presents another problem. This is particularly an issue when implementing certain post-manufacturing stages that require performing a chemical-mechanical polishing (CMP) step, as there would be a risk of clipping the components due to the difference in topography thus created on the substrate.
A need accordingly exists to allow for locally varying the thickness of the active silicon layer in an SOI substrate, while still maintaining the typical characteristics of the insulated substrate of this type of substrate and further maintaining the flatness of the surface state of this substrate.
Embodiments of the present invention provide a method for obtaining such a substrate.